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 MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MRFIC1806/D
The MRFIC Line
1.8 GHz PA Driver/Ramp
Designed primarily for use in DECT, Japan Personal Handy System (PHS), and other wireless Personal Communication Systems (PCS) applications. The MRFIC1806 includes a two stage driver amplifier and transmit waveform shaping circuitry in a low-cost SOIC-16 package. The amplifier portion employs depletion mode power GaAs MESFETs to produce +21 dBm output with 0 dBm input. The ramping circuit controls the burst-mode transmit rise and fall time and is adjustable through external components. This circuitry also places the amplifier in standby during TDMA receive mode. The MRFIC1806 is sized to drive the MRFIC1807 PA/Switch. Together with the rest of the MRFIC1800 GaAs ICs, this family offers the complete transmit and receive functions, less LO and filters, needed for a typical 1.8 GHz cordless telephone. * Usable 1500 - 2500 MHz * 23 dB Typical Gain * +21 dBm Typical 1.0 dB Compression * Simple Off-Chip Matching for Maximum Flexibility * 3.0 to 5.0 Volt Supply * Low Cost Surface Mount Plastic Package * Order MRFIC1806R2 for Tape and Reel. R2 Suffix = 2,500 Units per 16 mm, 13 inch Reel. * Device Marking = M1806
CASE 751B-05 (SO-16)
MRFIC1806
1.8 GHz DRIVER AMPLIFIER AND RAMP CIRCUIT GaAs MONOLITHIC INTEGRATED CIRCUIT
C1/VRAMP TX RAMP REG VDD GND GND RF IN VDD PCNTRL
1 20K 2 3 4 5 6 7 8 GATE BIAS LOGIC XLATOR VSS VDD RAMP
16 VDR 15 GND 14 VD1 13 GND 12 GND 11 RF OUT 10 GND 9 VSS
Figure 1. Pin Connections and Functional Block Diagram
REV 2
MOTOROLA (c) Motorola, Inc. 1997
MRFIC1806 1
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RECOMMENDED OPERATING RANGES ABSOLUTE MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Transmit Burst Enable Voltage (Low) Transmit Burst Enable Voltage (High) RF Input Power Bias Control Voltage Supply Voltage Supply Voltage Supply Voltage RF Input Frequency Thermal Resistance, Junction to Case Ambient Operating Temperature Storage Temperature Range Ramp Circuit Input Voltage (High) RF Input Power Bias Control Voltage Supply Voltage Supply Voltage Supply Voltage Rating Parameter REG VDD TX RAMP PCNTRL Symbol VDD VSS Tstg JC PIN TA REG VDD TX RAMP TX RAMP PCNTRL Symbol VDD VSS PIN fRF - 65 to +150 -10 to +70 Limit - 4.0 100 6.0 3.0 4.5 6.0 10 - 2.75 to - 2.25 - 0.2 to + 0.2 - 20 to + 5 2.8 to 3.5 0.5 to 1.5 2.9 to 3.1 3.0 to 5.0 1.5 - 2.5 Value C/W dBm Unit Vdc Vdc Vdc Vdc Vdc C C dBm GHz Unit Vdc Vdc Vdc Vdc Vdc Vdc
MRFIC1806 2
MOTOROLA
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DECT Application with Internal Logic Translator (See Figure 2. VDD = 3.5 V, REG VDD = 3.0 V, TA = 25C, VSS = - 2.5 V, TX RAMP = 3.0 V, PCNTRL set for Quiescent IDD = 120 mA, PIN = - 3.0 dBm @ 1.9 GHz unless otherwise stated.)
STANDBY MODE (TX RAMP = 0 V)
ELECTRICAL CHARACTERISTICS
MOTOROLA
Supply Current, REG IDD (Pin 3) Supply Current, ISS (Pin 9) Output Power Ramp Circuit Dynamic Range Supply Current, REG IDD (Pin 3) Supply Current, IDD (Pin 7) Supply Current, ISS (Pin 9) Output Third Order Intercept Harmonic Output Output Power Reverse Isolation Input Return Loss Small Signal Gain (PIN = - 7.0 dBm) RF IN 50 OHM 3 V (ON) TX RAMP 0 V (OFF) C9 1.5 pF
Figure 2. Applications Circuit Details for DECT using Internal Logic Translator
C7 4700 pF
T2 (FR4) Zo = 100 L = 8.5 mm
REG VDD 3.0 V
Characteristic
Characteristic
PCNTRL 1.4 V TYP
VDD 3.5 V
8
7
6
5
4
3
2
1
LOGIC XLATOR
VSS
GATE BIAS
VDD
20K
RAMP
Min
Min
40
18
21
--
--
--
--
--
--
--
--
--
--
C1 330 pF
14
15
16
10
12
13
11
9
0.25
0.35
19.5
- 25
- 36
Typ
Typ
115
0.4
0.6
44
33
36
12
23
R1 22K
C2 330 pF
C4 22 pF
R2 2.2
VSS - 2.5 V
C6 C5 1.5 pF 22 pF
Max
Max
C3 330 pF
135
0.4
0.6
0.9
0.6
T1 (FR4) Zo = 100 L = 20 mm
--
--
--
--
--
--
--
--
MRFIC1806 3
RF OUT 50 OHM dBm dBm dBm Unit Unit dBc mA mA mA mA mA dB dB dB dB
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Freq (GHz) 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5
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STANDBY MODE (VRAMP = - 2.4 V)
General Application without Internal Logic Translator (See Figure 3. VDD = 3.5 V, REG VDD (Pin 2) open, VSS = - 2.5 V, TX RAMP (Pin 2) grounded, VRAMP = 3.0 V, PCNTRL set for Quiescent IDD = 120 mA, PIN = 0 dBm @ 1.9 GHz, TA = 25C unless otherwise stated.)
ELECTRICAL CHARACTERISTICS
MRFIC1806 4
RF IN 50 OHM
Supply Current, ISS (Pin 9)
Output Power
Supply Current, IDD (Pin 7)
Supply Current, ISS (Pin 9)
Output Power (PIN = + 4.0 dBm)
Output Power (PIN = 0 dBm)
Small Signal Gain (PIN = - 7.0 dBm)
C9 1.5 pF
Figure 3. 1.9 GHz General Application Circuit Details (Internal Translator Disabled)
V RAMP
(VDD = 3.5 V, IDQ = 120 mA, TA = 25C, no matching circuit, reference plane at pins 6 and 11.)
T2 (FR4) Zo = 100 L = 8.5 mm
C7 4700 pF
0.521 0.541 0.560 0.571 0.581 0.592 0.607 0.636 0.620 0.654 0.734 Mag
Characteristic
Characteristic
VDD
PCNTRL 1.4 V TYP
R1 1K
S11
N/C
Angle
- 80.1 - 79.8 - 79.1 - 78.9 - 79.4 - 79.4 - 80.6 - 79.8 - 72.6 - 82.4 - 76.8 8 7 6 5 4 3 2 1
Table 1. Small Signal S - Parameters
10.88
10.77
12.25
13.01
11.17
13.11
Mag
6.90 7.80 7.95 9.30 9.64
LOGIC XLATOR
S21
VSS
GATE BIAS
- 174.9
- 165.1
- 151.3
- 137.0
- 109.4
- 117.4
Angle
- 87.9
147.2 155.7 166.9 174.1 VDD
20K
RAMP
Min
Min
20
21
--
--
--
--
--
0.042 0.033 0.029 0.026 0.024 0.019 0.017 0.014 0.012 0.009 0.011 Mag
S12
14
15
16
10
12
13
11
9
- 25
Typ
Typ
130
0.4
0.3
23
22
23
Angle
- 176
154 153 157 158 163 163 169 170 152 178
C4 22 pF
R2 2.2
VSS - 2.5 V
C6 C5 1.5 pF 22 pF
Max
Max
C3 330 pF
145
0.6
0.5
T1 (FR4) Zo = 100 L = 20 mm
--
--
--
--
0.445 0.442 0.432 0.429 0.432 0.427 0.421 0.423 0.344 0.326 0.278 Mag
S22
MOTOROLA
RF OUT 50 OHM dBm dBm dBm Unit Unit - 172.3 - 161.8 - 147.7 - 134.1 - 109.8 - 116.4 mA mA mA Angle dB - 98.9 161.7 164.6 171.1 178.8
DESIGN AND APPLICATIONS INFORMATION
DESIGN PHILOSOPHY The MRFIC1806 is designed to drive the MRFIC1807 Power Amplifier and Transmit/Receive Switch IC in Personal Communications System (PCS) applications such as Europe's DECT and Japan's Personal Handy System (PHS). The design incorporates not only a two-stage GaAs MESFET driver/exciter amplifier, but also externally controllable bias and ramping circuitry. The IC is designed to drive the MRFIC1807 with about +19 dBm which will, in turn, produce +26 dBm output, suitable for DECT. To reduce chip size (and cost) and to allow for flexibility of application, the amplifier has limited on-chip matching. The ramp circuitry is used to shape the drain voltage to the FETs for Time Domain Multiple Access (TDMA) applications and is comprised of a depletion mode pass device driven by a logic translator. Attack and release times are controllable through the use of external components. The IC is configured such that all, part or none of the ramping circuitry can be used, depending on the application. AMPLIFIER CIRCUIT APPLICATION As can be seen in Figures 2 and 3, the off-chip matching is straight forward. At frequencies near 1.9 GHz, the input requires 4.7 nH in series and 1.5 pF in shunt. The 4.7 nH series inductance may be implemented with a high- impedance transmission line as shown. The output, being close to 25 , requires only a shunt 1.5 pF capacitor. Drain voltage for stage 1 is supplied through pin 14 and for stage 2 through pin 11, the RF output. Pin 8, PCNTRL is used to set the quiescent bias point for both stages. While nominal IDDQ is 120 mA, it can be set as high as 180 mA for better linearity or lower for better efficiency. 120 mA is a good compromise for DECT and PHS. DECT, which employs GMSK constant envelope modulation can use RF amplifiers close to or in saturation without experiencing spectral regrowth of the signal. PHS, on the other hand, employs /4 DQPSK modulation which has some residual AM associated with the encoding. With AM present, RF amplifiers must be backed off from saturation so as not to regrow the filtered sidebands. The MRFIC1806 has plenty of backoff capability for PHS where the MRFIC1807 PA/switch must only produce about +21 dBm. With the 8.0 dB gain of the MRFIC1807, the MRFIC1806 need only produce +13 dBm output so the bias point can be reduced below the 120 mA suggested for DECT. As with all RF circuits, board layout and grounding are important. All RF signal paths must be controlled impedance structures. RF chip components must be high quality. Bypassing capacitors must be close to the IC and to ground vias. Pins which are designated as ground connections must be as close as possible to ground vias. RAMPING CIRCUIT OPTIONS The on-chip ramp circuit can be used to control the amplifier attack and release time for DECT applications through the use of a few external components as shown in Figure 2. This ramping is required to control the burst signal rise and fall time to avoid adjacent channel interference. At the same time, system specifications require the transmitter to reach full power in a minimum time. For DECT, it has been shown that a rise time of not greater than 2 microseconds will produce acceptable adjacent channel performance. The system requires full power in not greater than 10 microseconds. A good compromise, and the timing implemented in Figure 2, is 7 microseconds. The on-chip logic translator can be bypassed as shown in Figure 3 by applying a ramp voltage to Pin 1 through a 1.0 k resistor. This configuration allows flexibility in ramping the amplifier. The regulated VDD voltage is not required so current consumption can be reduced. - 2.3 V at Pin 1 turns the pass transistor, and the amplifier, off while a positive voltage will turn the pass transistor on. For full on state it is recommended that VRAMP be close to VDD. VRAMP can also be used to on-off key the amplifier for simple telemetry applications or as transmit/receive control. For more complex modulation schemes such as /4 DQPSK used in PHS, burst ramping can be implemented with the burst mode logic. Referring to Figure 3, the VRAMP voltage should be set to VDD to leave the pass transistor on. The on-chip pass transistor can also be bypassed and VDD applied to Pins 11 and 14. EVALUATION BOARDS Evaluation boards are available for RF Monolithic Integrated Circuits by adding a "TF" suffix to the device type. For a complete list of currently available boards and ones in development for newly introduced product, please contact your local Motorola Distributor or Sales Office.
MOTOROLA
MRFIC1806 5
21 20
22
21 OUTPUT POWER (dBm) OUTPUT POWER (dBm) 19 -10C 18 17 16 15 14 1.5 Pin = -3 dBm VDD = 3.5 V IDDQ = 120 mA 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 TA = 70C 25C 25C 20 -10C
19 Pin = 0 dBm VDD = 3.5 V IDDQ = 120 mA 1.7 TA = 70C
18
17 1.5
1.9 2.1 FREQUENCY (GHZ)
2.3
2.5
Figure 4. Output Power versus Frequency With Internal Logic Translator
Figure 5. Output Power versus Frequency Without Internal Logic Translator
20 5.0 V 19 OUTPUT POWER (dBm) 18 17 16 15 14 1.5 Pin = - 3 dBm TA = 25C PCNTRL = 1.5 V 1.7 1.9 2.1 FREQUENCY (GHz) 2.3 2.5 VDD = 3.0 V OUTPUT POWER (dBm) 3.5 V
23 3.5 V 22 5V Pin = 0 dBm TA = 25C PCNTRL = 1.5 V
21 VDD = 3 V 20
19 18 1.5
1.7
1.9 2.1 FREQUENCY (GHz)
2.3
2.5
Figure 6. Output Power versus Frequency With Internal Logic Translator
Figure 7. Output Power versus Frequency Without Internal Translator
22 18 OUTPUT POWER (dBm) 14 10 6 2 12 -10 VDD = 3.5 V f = 1.9 GHz TA = 25C 0 2 1.0 V
25 2.0 V 1.0 V
1.5 V OUTPUT POWER (dBm)
20
15
10 PCNTRL = 0.5 V 5 VDD = 3.5 V f = 1.9 GHz TA = 25C -5 0 INPUT POWER (dBm) 5
PCNTRL = 0.5 V -8 -2 -6 -4 INPUT POWER (dBm)
0 -10
Figure 8. Output Power versus Input Power With Internal Logic Translator
Figure 9. Output Power versus Input Power Without Internal Logic Translator
MRFIC1806 6
MOTOROLA
22
24 22 -10C OUTPUT POWER (dBm) -10C 20 18 16 14 12 -10 TA = 25C f = 1.9 GHz VDD = 3.5 V IDDQ = 120 mA 5 70C 70C
20 OUTPUT POWER (dBm)
18
16 TA = 25C f = 1.9 GHz VDD = 3.5 V IDDQ = 120 mA 0 2
14
12 -10
-8
-2 -6 -4 INPUT POWER (dBm)
-5 0 INPUT POWER (dBm)
Figure 10. Output Power versus Input Power With Internal Logic Translator
Figure 11. Output Power versus Input Power Without Internal Logic Translator
22 5.0 V
26 24 5.0 V
20 OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
VDD = 3.0 V
22 3V 20 18 16 14 f = 1.9 GHz TA = 25C PCNTRL = 1.5 V -5 0 INPUT POWER (dBm) 5 VDD = 3.5 V
18 3.5 V 16 f = 1.9 GHz TA = 25C PCNTRL = 1.5 -8 -6 -4 -2 INPUT POWER (dBm) 0 2
14
12 -10
12 -10
Figure 12. Output Power versus Input Power With Internal Logic Translator
Figure 13. Output Power versus Input Power Without Internal Logic Translator
150 140 SUPPLY CURRENT (mA) 130 25C 120 110 TA = 10C 100 90 1.5 VDD = 3.5 V Pin = -3 dBm IDDQ = 120 mA
200 VDD = 3.5 V IDDQ = 120 mA Pin = 0 dBm
SUPPLY CURRENT (mA)
70C
180
70C
160 25C 140 -10C 120 70C -10C
1.7
1.9 2.1 FREQUENCY (GHz)
2.3
2.5
100 1.5
1.7
1.9 2.1 FREQUENCY (GHz)
2.3
2.5
Figure 14. Supply Current versus Frequency With Internal Logic Translator
Figure 15. Supply Current versus Frequency Without Internal Logic Translator
MOTOROLA
MRFIC1806 7
150 140 SUPPLY CURRENT (mA) 130 5V 120 110 VDD = 3.0 V 100 90 1.5 3.5 V Pin = -3 dBm TA = 25C PCNTRL = 1.5 V
210 190 SUPPLY CURRENT (mA) 170 150 130 110 90 1.5 VDD = 3.0 V 5.0 V 3.5 V Pin = 0 dBm TA = 25C PCNTRL = 1.5 V
1.7
1.9 2.1 FREQUENCY (GHz)
2.3
2.5
1.7
1.9 2.1 FREQUENCY (GHz)
2.3
2.5
Figure 16. Supply Current versus Frequency With Internal Logic Translator
Figure 17. Supply Current versus Frequency Without Internal Logic Translator
126 124 SUPPLY CURRENT (mA) 122 120 118 116 114 112 70C 110 108 -10 -8 -2 -6 -4 INPUT POWER (dBm) 0 2 TA = 10C f = 1.9 GHz VDD = 3.5 V IDDQ = 120 mA 25C OUTPUT POWER (dBm) 70C
150 f = 1.9 GHz VDD = 3.5 V IDDQ = 120 mA
140
TA = 25C 70C
130
120 -10C 110 100 -10
-8
-6
-2 -4 INPUT POWER (dBm)
0
2
4
Figure 18. Supply Current versus Input Power With Internal Translator
Figure 19. Supply Current versus Input Power Without Internal Translator
130 125 SUPPLY CURRENT (mA) 120 115 5.0 V 110 3.5 V 105 100 -10 VDD = 3.0 V -6 -4 -2 INPUT POWER (dBm) f = 1.9 GHz TA = 25C PCNTRL = 1.5 V
170 160 SUPPLY CURRENT (mA) 150 140 130 120 VDD = 3 V 110 -8 0 2 100 -10 -8 -6 -4 -2 INPUT POWER (dBm) 0 2 4 3.5 V f = 1.9 GHz PCNTRL = 1.5 V TA = 25C
5V
Figure 20. Supply Current versus Input Power With Internal Translator
Figure 21. Supply Current versus Input Power Without Internal Logic Translator
MRFIC1806 8
MOTOROLA
225 200 I DD, SUPPLY CURRENT (mA) 175 150 125 100 75 50 25 0.5 0.75 1 1.5 1.25 PCNTRL (Volts) 1.75 2 70C -10C TA = 25C f = 1.9 GHz Pin = 0 dBm
23 21 Pout , OUTPUT POWER (dBm) 19 17 15 13 10C 11 9 0.5 0.75 1 1.5 1.25 PCNTRL (Volts) f = 1.9 GHz Pin = 0 dBm 70C 25C
1.75
2
Figure 22. Supply Current versus PCNTRL Without Internal Logic Translator
Figure 23. Pout versus PCNTRL Without Internal Logic Translator
25 24 SMALL SIGNAL GAIN (dBm) 23 22 21 20 19 18 17 1.5 Pin = 7 dBm VDD = 3.5 V IDDQ = 120 mA 1.7 1.9 2.1 f, FREQUENCY (GHz) 2.3 2.5 TA = 70C 25C SMALL SIGNAL GAIN (dB) -10C
25 24 23 22 21 20 19 18 17 1.5 Pin = 7 dBm VDD = 3.5 V IDDQ = 120 mA 1.7 1.9 2.1 f, FREQUENCY (GHz) 2.3 2.5 TA = 70C 25C -10C
Figure 24. Small Signal Gain versus Frequency With Internal Logic Translator
Figure 25. Small signal Gain versus Frequency Without Internal Logic Translator
I DDQ, QUIESCENT SUPPLY CURRENT (mA)
55 -10C 50 TA = 25C 45 70C 40 Pin = - 3 dBm VDD = 3.5 V IDDQ = 120 mA
300 250 200 150 100 50 0 0.5 TA = 25C & -10C 70C f = 1.9 GHz VDD = 3.5 V
RF DYNAMIC RANGE (dB)
35 1.5
1.7
1.9 2.1 f, FREQUENCY (GHz)
2.3
2.5
0.75
1
1.25 1.5 PCNTRL (Volts)
1.75
2
Figure 26. Dynamic Range versus Frequency With Internal Logic Translator
Figure 27. Quiescent Supply Current versus PCNTRL With Internal Logic Translator
MOTOROLA
MRFIC1806 9
24 21 18 15 12 9 6 -10 600 kHz ACPR 900 kHz ACPR -8 -6 -4 -2 0 PIN, INPUT POWER (DBM) 2 4 f = 1.9 GHz VDD = 3.5 V IDDQ = 120 mA TA = 25C Mod = 384 kb/s /4 DQPSK
-45 -50 -55 ACPR (dBc) -60 -65 -70 -75
22 CW P , OUTPUT POWER (dBm) out 20 Burst 18
P , OUTPUT POWER (dBm) out
Pout
16 VDD = 3.5 V Freq = 1.9 GHz IDDQ = 120 mA
14
12 -10
-8
-6 -4 PIN, INPUT POWER (DBM)
-2
0
Figure 28. Output Power and Adjacent Channel Power Ratio versus Input Power Without Internal Logic Translator
Figure 29. Continuous and Burst Mode Output Power versus Input Power With Internal Logic Translator
MRFIC1806 10
MOTOROLA
PACKAGE DIMENSIONS
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
CASE 751B-05 ISSUE J
MOTOROLA
MRFIC1806 11
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps
MRFIC1806 12
MOTOROLA MRFIC1806/D


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